Memory Fence on MIPS

Anton Kirilov akirilov at minervanetworks.com
Tue Feb 21 16:59:39 CET 2012


Hello,

I have attached my implementation of a memory fence on MIPS. Unfortunately, I have been unable to test it extensively, since I only have access to MIPS-based SoCs that are single core, but I have based it on the MIPS32 architecture manual ( 
http://mips.com/products/architectures/mips32/#specifications ), and the code is consistent with what is generated by GCC. Actually, it is the same for MIPS64.

Would you, please, merge it into the libev source code?

Yours faithfully,
Anton Kirilov

--- ev.c.orig	2012-02-21 06:34:02.000000000 +0200
+++ ev.c	2012-02-21 17:42:30.814975031 +0200
@@ -579,6 +579,8 @@
       #define ECB_MEMORY_FENCE_RELEASE __asm__ __volatile__ ("membar #LoadStore |             #StoreStore")
     #elif defined(__s390__) || defined(__s390x__)
       #define ECB_MEMORY_FENCE         __asm__ __volatile__ ("bcr 15,0" : : : "memory")
+    #elif defined(__mips)
+      #define ECB_MEMORY_FENCE         __asm__ __volatile__ ("sync" : : : "memory")
     #endif
   #endif
 #endif



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