Feature request: ability to use libeio with multiple event loops

[Ben Noordhuis]

On Wed, Dec 21, 2011 at 04:19, Marc Lehmann <schmorp at schmorp.de> wrote:
> On Wed, Dec 21, 2011 at 03:37:48AM +0100, Ben Noordhuis <info at bnoordhuis.nl> wrote:
>> You either have an overly broad definition of or simply the wrong idea
>> about what CPU registers are.
>
> Then you can surely point out where my idea differs from, say, intel's or
> motorola's idea of what registers are. Please do so, I am very curious.
>
> Or do you mean to say that everybody is just wrong about registers, except
> you? It surely sounds like that to me.
>
>> What do you think happens when a thread on a UP system is swapped for
>> another one?
>
> I am sure that wikipedia has a good entry-level introduction somewhere, if
> you want to find out and learn something, it's not all that difficult.
>
>> The benefit that threads have over processes on UP systems is that
>> they share the same address space.
>
> That makes no sense - they do so on multiprocessor too, but thats not what
> threads were invented for, nor their benefit on UP. Hint, the benefit
> is improved context switch times due to not having to change e.g. mmu
> registers.
>
> Or just use your brain for a change - processes can share memory, too, so
> if thats the benefit they give on UP, why again were they invented?
>
> Try google, it's not all that hard to find out why threads were invented.
> Don't weasel out by changing the definition of a thread, prove that you
> can do your homework.
>
>> There should be no or fewer TLB misses provided the operating system
>> doesn't flush the TLB cache on each task switch.
>
> Whats a task switch for you exactly, if not a context switch?
>
>> But guess what, that's something x86_64 linux kernels always
>> do. Apparently it's faster than invalidating ranges of individual pages.
>
> If x86_64 kernels flush the tlb cache on each context switch then there would
> be little advantage to using threads on uniprocessor indeed.
>
> Now, you don't normally need to invalidate page ranges on context
> switches, though, so I am not sure you mean context switch when you talk
> about task switch.
>
> Maybe you have simply the wrong idea about what a context switch is or how
> a cpu or mmu works.

Well put in a nicely condescending tone. Still, you haven't told me
what your idea of CPU registers is or how they magically stay intact
across a task switch. Please enlighten me.

Re: task switch vs. context switch: I'm using linux kernel
nomenclature because it's (IMO) more precise than the overloaded
concept of a context switch. I know you've posted to the LKML once or
twice so I assume you have a basic grasp of the kernel's internals.